1. Technical Field
The embodiments described here relate to a semiconductor integrated circuit (IC) and, more particularly, a semiconductor IC that includes a clock buffer.
2. Related Art
Generally, a synchronous memory operates in synchronization with a clock signal. A high-speed synchronous memory, such as a double data rate (DDR) memory, employs a delay locked loop (DLL) circuit to delay or fix an external clock signal such that data adjustably synchronizes with the clock signal. For example, a clock tree unit receives a clock signal to relay the clock signal to data input/output (I/O) buffers and data I/O pins. However, as a clock distribution path of the clock tree unit is increased, the load of the clock signal increases due to the loading of circuits interposed between the clock tree unit and the data I/O pins. Thus, if a clocking range or a swing range of a clock signal is changed due to the variation of an external voltage, power noise (jitter) may occur in clock signals that passed through the clock tree unit. Accordingly, transmission of the clock signals to the clock tree unit must minimize the power noise to prevent inaccurate or false data from being sent to or received from a semiconductor memory.